1) Field of the Invention
This invention relates generally to fabrication of semiconductor devices and more particularly to the fabrication of a MIM capacitor and conductive lines.
2) Description of the Prior Art
There are many types of capacitor structures for semiconductor integrated circuits, such as metal-oxide-semiconductor (MOS) capacitors, PN junction capacitors, and polysilicon-insulator-polysilicon (PIP) capacitors. Each of these capacitor structures includes at least one monocrystalline silicon layer or polycrystalline silicon layer which is used as a capacitor electrode. The use of silicon for the capacitor electrode, however, may result in a higher electrode resistance than is desired.
It is thus desirable to reduce the resistance of capacitor electrodes to decrease frequency dependence of the capacitor. Accordingly, metal-insulator-metal (MIM) thin film capacitors have been developed to provide low electrode resistances. Moreover, metal-insulator-metal capacitors can be used in integrated circuits requiring high speed performance. In addition, metal-insulator-metal thin film capacitors have been applied to advanced analog semiconductor devices because these capacitors have capacitance fluctuation rates dependent on voltage and temperature which are sufficiently low to provide desirable electrical characteristics.
In addition, there have been efforts to reduce thicknesses of dielectric layers for integrated circuit capacitors to thereby increase the performance of capacitors including these thinner dielectric layers. In particular, the capacitance of a capacitor can be increased by reducing the thickness of the dielectric layer between the two electrodes of the capacitor. There have also been efforts to increase capacitances by using dielectric layers having relatively high dielectric constants, and by increasing the surface areas of the capacitor electrodes. Furthermore, multi-wiring or multilevel interconnect processes have been applied to semiconductor manufacturing methods to facilitate the development of high-density integration and microelectronic technology.
Thus it is very necessary to provide a novel process of forming MIM capacitors which can provide a new structure of the MIM capacitors having large capacitance as well as high integration of the integrated circuit.
The inventors have found that with the standard CMOS technology being applied in mixed signal and analog integrated circuits arena, more and more passive elements are required for various applications. Due to its good performance and simplicity of integration with CMOS technology, metal-insulator-metal {MIM} capacitor is widely used for analog and RF purposes. However, due to its nature of backend processing, the dielectric thickness used in MIM is much higher than poly-insulator-poly (PIP) and polyinsulator-substrate (PIS) capacitors. This leads to lower specific capacitance (capacitance per unit area) for MIM capacitor, When used for RF application, higher specific capacitance, which means smaller area for a given capacitance value, becomes more important when low coupling noise between the MIM and substrate is considered semiconductor.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering U.S. Pat. No. 6,387,750B1(Lai et al.) shows a process for a MIM capacitor.
U.S. Pat. No. 6,559,004b1(Yang et al.) shows a process for forming a MIM capacitor.
U.S. Pat. No. 6,468,873b1(Lui et al. al.) shows a CU MIM process.
US 2002/0019123A1xe2x80x94Ma et al. discloses a Cu MIM process.
U.S. Pat. No. 6,426,250 (Lee,et al.) shows a High density stacked MIM capacitor structure.
U.S. Pat. No. 6,451,650 (Lou) discloses a Low thermal budget method for forming MIM capacitors.
An embodiment of the present invention provides a method of manufacturing a MIM capacitor which is characterized as follows.
We provide a semiconductor structure having a first region and a capacitor region. Next we form a conductive layer over the semiconductor structure. The first conductive layer is patterned to form a plurality of trenches in the capacitor region. We form a capacitor dielectric layer over the first conductive layer. Next, we form a top plate over the capacitor dielectric layer in the capacitor region to form a capacitor. The first conductive layer in the first region is patterned to form conductive patterns and a bottom plate. An interlevel dielectric layer is formed over the first conductive layer.
Additional objects and advantages of the invention will be set forth in the description that follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of instrumentalities and combinations particularly pointed out in the append claims.